Design a single trace route consisting of on-chip and off-chip interconnect spanning two FR4 layers and characterize it for a PCI Express 6.0[1] serial data link.

Design a single trace route consisting of on-chip and off-chip interconnect spanning two FR4 layers and characterize it for a PCI Express 6.0[1] serial data link.

Problem Outline:

PCI Express 6.0 is an upgrade of PCI Express (PCIe), a high-speed serial data interconnect framework for, e.g. graphics communications. PCIe bus consists of 16 lanes, whereas each lane contains two differential signal pairs (for transmit and receive), thus a total of four signal traces comprise one lane. This project assignment focuses on modeling signal propagation through only one such trace, i.e. on modeling one half of a differential signal pair (or ¼ of one lane or 1/64 of a full PCIe bus). Assume that PCIe 6.0 will use copper as the signal trace material and FR4 for the dielectric material of the board. The operating data transfer speed for PCIe 6.0 is set at approximately 8 GB/sec, which corresponds to a single UI (unit interval) of 125 ps (see more explanation below on p. 4). Unlike the actual signaling scheme PCIe 6.0 (PAM-4), a simpler binary scheme will be utilized in this project.